The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimensions of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, for example on the order of 1.000 xc3x85 or less thick are generally required for acceptable performance in short channel devices.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silicide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the xe2x80x9csalicidexe2x80x9d process.
A portion of a typical semiconductor device 40 is schematically illustrated in FIG. 1A and comprises a silicon-containing substrate 4 with source/drain 30 regions formed therein. Gate oxide 10 and gate electrode 12 are formed on the silicon-containing substrate 4. Sidewall spacers 14 are formed on opposing side surfaces 13 of gate electrode 12. Sidewall spacers 14 typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers 14 mask the side surfaces 13 of the gate 12 w hen metal layer 22 is deposited, thereby preventing silicide from forming on the gate electrode side surfaces 13.
After metal layer 22 is deposited. heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode 12 and substrate surface 5 to form conductive metal silicide contacts 24 (FIG. 1B). After the metal silicide contacts 24 are formed, the unreacted metal 22 is removed by etching, as with a wet etchant, e.g., an aqueous H2O2/NH4OH solution. The sidewall spacer 14, therefore, functions as an electrical insulator separating the silicide contact 24 on the gate electrode 12 from the metal silicide contacts 24 on the source/drain regions 30, as shown in FIG. 1B.
Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create silicides (TiSi2, CoSi2) when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi2 layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi2 is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi2 initially forms a high resistivity phase (C49), and transformation from C49 to a low resistivity phase (C54) is nucleation limited, i.e., a high temperature is required to effect the phase change.
Cobalt silicide, unlike TiSi2, exhibits less linewidth dependence of sheet resistance. However, CoSi2 consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with silicon on insulator (SOI) substrates. Without enough Si to react with Co to form CoSi2, a thin layer of CoSi2 results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material, thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi2 and CoSi2 because many limitations associated with TiSi2 and CoSi2 are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni and Co through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi2 and CoSi2 are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi2 and CoSi2. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
Although the use of NiSi in salicide technology has certain advantages over utilizing TiSi2 and CoSi2, there are problems using NiSi in certain situations. Forming NiSi on doped, crystallized Si usually produces a smooth interface between the NiSi layer and the doped, crystallized Si layer. However, when crystallized Si is doped with arsenic (As), a rough interface between the NiSi and the doped, crystallized Si forms, which leads to certain problems.
FIG. 2 illustrates the degree of interface 36 roughness between a conventional nickel silicide (NiSi) contact 24 and arsenic doped source/drain region 30. In this system, the mean peak to valley interface roughness height d is about 300 xc3x85 to about 400 xc3x85. This large degree of interface roughness can cause a variety of electrical problems such as spiking and increased junction leakage. The interface roughness could penetrate all the way through the source/drain region in a shallow junction device, causing a local short circuit, thereby resulting in junction leakage. In order to prevent these problems, a thinner metal layer can be deposited, thereby resulting in a thinner silicide layer, or the depth of source/drain junction can be increased. However, neither of these approaches is satisfactory: the former approach would result in higher sheet resistance and a slower semiconductor device, and the latter approach runs counter to the trend toward smaller device dimensions, both vertically, and laterally, in order to increase switching speeds.
Interface roughness becomes more pronounced as the concentration of the dopant increases. In an As doped device with NiSi contacts, interface roughness is especially a problem where the peak concentration of the doped arsenic is in the vicinity of the upper surface of the source/drain regions. In a typical arsenic doped MOS device the arsenic ions will be implanted with an energy and dose of 10 to 20 keV and 1xc3x971015 to 6xc3x971015 ions/cm2, which results in a peak arsenic concentration at about 200 xc3x85 to about 400 xc3x85 below the upper surface of the source/drain region. When the peak arsenic concentration is located in this region an unacceptably high degree of interface roughness results when nickel silicide is formed.
Implanting the arsenic ions deeper into the silicon substrate reduces the interface roughness. However, this has been avoided in conventional practice. A Gaussian type distribution of dopant concentration versus implant into depth is obtained when dopants are implanted into bulk silicon substrates. Driving the peak concentration of the dopant deeper into the bulk silicon substrate to overcome the interface roughness effects shifts more of the dopant even deeper into the substrate. In a bulk silicon substrate, deep implantation of dopant to overcome the silicide interface roughness problem results in slower, larger-dimension devices.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising semiconductors.
There exists a need in the semiconductor device art to provide silicide contacts for planar transistors which overcome the problem of silicide contact-source/drain region interface roughness. There exists a need in this art to deeply implant dopant in the source/drain regions to prevent silicide interface roughness while maintaining the desirable dimensional and electrical characteristics of shallow implantation. There exists a need in this art to provide arsenic doped source/drain regions with nickel silicide contacts without an unacceptably high degree of silicide-source/drain interface roughness.
These and other needs are met by embodiments of the present invention, which provide a method of manufacturing a semiconductor device comprising providing a silicon-containing substrate having an upper surface. The substrate is doped by ion implantation to form source/drain regions such that the concentration of the dopant and the depth below the upper surface of the implant substantially reduce interface roughness between subsequently formed nickel silicide contacts and the source/drain regions. A nickel layer is deposited over the upper surface of the substrate and the nickel layer is heated so that the nickel layer reacts with the silicon layer to form nickel silicide contacts.
The earlier stated needs are also meet by other embodiments of the instant invention that provide a semiconductor device comprising a silicon-containing substrate having an upper surface. The silicon-containing substrate contains doped source/drain regions and nickel silicide contacts, wherein the doping concentration and depth below the upper surface of the substrate are such that interface roughness between nickel silicide contacts and the source/drain regions is substantially reduced with respect to conventional semiconductor devices comprising nickel silicide contacts.
The earlier stated needs are further met by other embodiments of the instant invention that provide a method of manufacturing a semiconductor device comprising providing a silicon on insulator substrate comprising an insulating layer on a substrate base and a silicon layer is on the insulating layer. A gate oxide layer and conductive gate material are, in turn, formed over the silicon layer. The gate material layer and gate oxide layer are then patterned to form a gate electrode having an upper surface and opposing side surfaces. An insulating material is deposited over the gate electrode and silicon layer. The insulating material is patterned to form sidewall spacers on the opposing sides of the gate electrode. Source/drain implants are formed by ion implanting a dopant into the silicon layer, such that the dopant concentration and depth significantly reduces the interface roughness between subsequently formed nickel silicide contacts and source/drain regions. The source/drain implants are subsequently heated to activate the source/drain regions and then a nickel layer is deposited over the gate electrode and source/drain regions. The nickel layer is heated so that the nickel reacts to form nickel silicide contacts with the underlying silicon on the gate electrode and source/drain regions. The unreacted portions of the nickel layer are removed from the device.
This invention addresses the needs for an improved method of forming high conductivity silicide contacts to source/drain regions and gate electrodes with reduced silicide interface roughness and improved electrical characteristics. The present invention reduces the possibility of spiking and junction leakage.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.